Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator

Abhinav S. Mansingka, Ahmed G. Radwan, Khaled N. Salama, Mohammed A. Zidan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Scopus citations


This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.
Original languageEnglish (US)
Title of host publication2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Print)9781612848563
StatePublished - Sep 28 2011

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01


Dive into the research topics of 'Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator'. Together they form a unique fingerprint.

Cite this