Spatial pooler is responsible for feature extraction in Hierarchical Temporal Memory (HTM). In this paper, we present analog backpropagation learning circuits integrated to the memristive circuit design of spatial pooler. Using 0.18μm CMOS technology and TiOx memristor models, the maximum on-chip area and power consumption of the proposed design are 8335.074μm2 and 51.55mW, respectively. The system is tested for a face recognition problem AR face database achieving a recognition accuracy of 90%.
|Original language||English (US)|
|Title of host publication||Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|State||Published - Mar 1 2019|