An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications

Raunak Borwankar; Mohammad R. Haider; Reinhold Ludwig; Yehia Massoud

doi:10.1109/MWSYM.2018.8439410

An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications

Raunak Borwankar, Mohammad R. Haider, Reinhold Ludwig, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A high gain, ultra-low-power mixer in 45 nm standard CMOS process is presented. The mixer is designed by using coupling capacitors across drain-gate of the transconductance stages. The proposed mixer achieves a conversion gain of 18.5 dB and noise-figure of 19.2 dB at LO power of 0 dBm. The mixer achieves 14.5 dBm IIP3 and -16.2 dB P 1dB for RF signal of 5.9 GHz. Operating at 0.4 V supply, the mixer consumes 170 μ W power for RF frequencies of 2.4-5.9 GHz. The layout area of mixer core is 0.0046 mm2. Post-layout simulations demonstrate that the proposed design achieves a very high figure-of-merit when compared to other state-of-the-art down-conversion CMOS mixers.

Original language	English (US)
Title of host publication	IEEE MTT-S International Microwave Symposium Digest
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	822-824
Number of pages	3
ISBN (Print)	9781538650677
DOIs	https://doi.org/10.1109/MWSYM.2018.8439410
State	Published - Aug 17 2018
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/MWSYM.2018.8439410

Cite this

@inproceedings{f7e58d910fee43d18c17005fefb4eea6,

title = "An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications",

abstract = "A high gain, ultra-low-power mixer in 45 nm standard CMOS process is presented. The mixer is designed by using coupling capacitors across drain-gate of the transconductance stages. The proposed mixer achieves a conversion gain of 18.5 dB and noise-figure of 19.2 dB at LO power of 0 dBm. The mixer achieves 14.5 dBm IIP3 and -16.2 dB P 1dB for RF signal of 5.9 GHz. Operating at 0.4 V supply, the mixer consumes 170 μ W power for RF frequencies of 2.4-5.9 GHz. The layout area of mixer core is 0.0046 mm2. Post-layout simulations demonstrate that the proposed design achieves a very high figure-of-merit when compared to other state-of-the-art down-conversion CMOS mixers.",

author = "Raunak Borwankar and Haider, {Mohammad R.} and Reinhold Ludwig and Yehia Massoud",

note = "Generated from Scopus record by KAUST IRTS on 2022-09-13",

year = "2018",

month = aug,

day = "17",

doi = "10.1109/MWSYM.2018.8439410",

language = "English (US)",

isbn = "9781538650677",

pages = "822--824",

booktitle = "IEEE MTT-S International Microwave Symposium Digest",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

TY - GEN

T1 - An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications

AU - Borwankar, Raunak

AU - Haider, Mohammad R.

AU - Ludwig, Reinhold

AU - Massoud, Yehia

N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13

PY - 2018/8/17

Y1 - 2018/8/17

N2 - A high gain, ultra-low-power mixer in 45 nm standard CMOS process is presented. The mixer is designed by using coupling capacitors across drain-gate of the transconductance stages. The proposed mixer achieves a conversion gain of 18.5 dB and noise-figure of 19.2 dB at LO power of 0 dBm. The mixer achieves 14.5 dBm IIP3 and -16.2 dB P 1dB for RF signal of 5.9 GHz. Operating at 0.4 V supply, the mixer consumes 170 μ W power for RF frequencies of 2.4-5.9 GHz. The layout area of mixer core is 0.0046 mm2. Post-layout simulations demonstrate that the proposed design achieves a very high figure-of-merit when compared to other state-of-the-art down-conversion CMOS mixers.

AB - A high gain, ultra-low-power mixer in 45 nm standard CMOS process is presented. The mixer is designed by using coupling capacitors across drain-gate of the transconductance stages. The proposed mixer achieves a conversion gain of 18.5 dB and noise-figure of 19.2 dB at LO power of 0 dBm. The mixer achieves 14.5 dBm IIP3 and -16.2 dB P 1dB for RF signal of 5.9 GHz. Operating at 0.4 V supply, the mixer consumes 170 μ W power for RF frequencies of 2.4-5.9 GHz. The layout area of mixer core is 0.0046 mm2. Post-layout simulations demonstrate that the proposed design achieves a very high figure-of-merit when compared to other state-of-the-art down-conversion CMOS mixers.

UR - https://ieeexplore.ieee.org/document/8439410/

UR - http://www.scopus.com/inward/record.url?scp=85053026994&partnerID=8YFLogxK

U2 - 10.1109/MWSYM.2018.8439410

DO - 10.1109/MWSYM.2018.8439410

M3 - Conference contribution

SN - 9781538650677

SP - 822

EP - 824

BT - IEEE MTT-S International Microwave Symposium Digest

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications

Abstract

Bibliographical note

UN SDGs

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