TY - JOUR
T1 - An interconnect-free micro-electromechanical 7-bit arithmetic device for multi-operand programmable computing
AU - zou, xuecui
AU - Yaqoob, Usman
AU - Ahmed, Sally
AU - Wang, Yue
AU - Salama, Khaled N.
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2023-04-11
PY - 2023/4/3
Y1 - 2023/4/3
N2 - Computational power density and interconnection between transistors have grown to be the dominant challenges for the continued scaling of complementary metal–oxide–semiconductor (CMOS) technology due to limited integration density and computing power. Herein, we designed a novel, hardware-efficient, interconnect-free microelectromechanical 7:3 compressor using three microbeam resonators. Each resonator is configured with seven equal-weighted inputs and multiple driven frequencies, thus defining the transformation rules for transmitting resonance frequency to binary outputs, performing summation operations, and displaying outputs in compact binary format. The device achieves low power consumption and excellent switching reliability even after 3 × 103 repeated cycles. These performance improvements, including enhanced computational power capacity and hardware efficiency, are paramount for moderately downscaling devices. Finally, our proposed paradigm shift for circuit design provides an attractive alternative to traditional electronic digital computing and paves the way for multioperand programmable computing based on electromechanical systems.
AB - Computational power density and interconnection between transistors have grown to be the dominant challenges for the continued scaling of complementary metal–oxide–semiconductor (CMOS) technology due to limited integration density and computing power. Herein, we designed a novel, hardware-efficient, interconnect-free microelectromechanical 7:3 compressor using three microbeam resonators. Each resonator is configured with seven equal-weighted inputs and multiple driven frequencies, thus defining the transformation rules for transmitting resonance frequency to binary outputs, performing summation operations, and displaying outputs in compact binary format. The device achieves low power consumption and excellent switching reliability even after 3 × 103 repeated cycles. These performance improvements, including enhanced computational power capacity and hardware efficiency, are paramount for moderately downscaling devices. Finally, our proposed paradigm shift for circuit design provides an attractive alternative to traditional electronic digital computing and paves the way for multioperand programmable computing based on electromechanical systems.
UR - http://hdl.handle.net/10754/690966
UR - https://www.nature.com/articles/s41378-023-00508-0
U2 - 10.1038/s41378-023-00508-0
DO - 10.1038/s41378-023-00508-0
M3 - Article
C2 - 37025566
SN - 2055-7434
VL - 9
JO - Microsystems & Nanoengineering
JF - Microsystems & Nanoengineering
IS - 1
ER -