An Efficient Topology-Based Algorithm for Transient Analysis of Power Grid

Lan Yang, Jingbin Wang, Lorenzo Azevedo, Jim Jing-Yan Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In the design flow of integrated circuits, chip-level verification is an important step that sanity checks the performance is as expected. Power grid verification is one of the most expensive and time-consuming steps of chip-level verification, due to its extremely large size. Efficient power grid analysis technology is highly demanded as it saves computing resources and enables faster iteration. In this paper, a topology-base power grid transient analysis algorithm is proposed. Nodal analysis is adopted to analyze the topology which is mathematically equivalent to iteratively solving a positive semi-definite linear equation. The convergence of the method is proved.
Original languageEnglish (US)
Title of host publicationIntelligent Computing Theories and Methodologies
PublisherSpringer Nature
Number of pages12
ISBN (Print)9783319221793
StatePublished - Aug 11 2015

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01


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