An alternative organization of defect map for defect-resilient embedded on-chip memories

Kang Yi; Shih Yang Cheng; Young Hwan Park; Fadi Kurdahi; Ahmed Eltawil

An alternative organization of defect map for defect-resilient embedded on-chip memories

Kang Yi, Shih Yang Cheng, Young Hwan Park, Fadi Kurdahi, Ahmed Eltawil

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose the low power and low area defect map organization for the defect-resilient embedded memory system for multimedia SOCs. Existing approach to build defect map of embedded memories is based on the CAM (Content Addressable Memory) organization. But, it consumes too much power and relatively large chip area. It may be serious problem in the near future for very deep submicron technologies. Therefore, we propose the SRAM-based defect map organization to reduce both the power consumption and chip area. We also develop new defect map access algorithm to minimize the number of defect map access operations to save power. Our estimation results show the new scheme based on SRAM defect map organization consumes only 1/4 times of power at BER=1.0% compared with the power overhead by the existing approach. © Springer-Verlag Berlin Heidelberg 2007.

Original language	English (US)
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
State	Published - Dec 1 2007
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2019-11-20

Cite this

@inproceedings{43b71ef6083f4bebaf9e07ba9b232f5c,

title = "An alternative organization of defect map for defect-resilient embedded on-chip memories",

abstract = "In this paper, we propose the low power and low area defect map organization for the defect-resilient embedded memory system for multimedia SOCs. Existing approach to build defect map of embedded memories is based on the CAM (Content Addressable Memory) organization. But, it consumes too much power and relatively large chip area. It may be serious problem in the near future for very deep submicron technologies. Therefore, we propose the SRAM-based defect map organization to reduce both the power consumption and chip area. We also develop new defect map access algorithm to minimize the number of defect map access operations to save power. Our estimation results show the new scheme based on SRAM defect map organization consumes only 1/4 times of power at BER=1.0% compared with the power overhead by the existing approach. {\textcopyright} Springer-Verlag Berlin Heidelberg 2007.",

author = "Kang Yi and Cheng, {Shih Yang} and Park, {Young Hwan} and Fadi Kurdahi and Ahmed Eltawil",

note = "Generated from Scopus record by KAUST IRTS on 2019-11-20",

year = "2007",

month = dec,

day = "1",

language = "English (US)",

isbn = "9783540743088",

booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

An alternative organization of defect map for defect-resilient embedded on-chip memories. / Yi, Kang; Cheng, Shih Yang; Park, Young Hwan et al.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2007.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An alternative organization of defect map for defect-resilient embedded on-chip memories

AU - Yi, Kang

AU - Cheng, Shih Yang

AU - Park, Young Hwan

AU - Kurdahi, Fadi

AU - Eltawil, Ahmed

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2007/12/1

Y1 - 2007/12/1

N2 - In this paper, we propose the low power and low area defect map organization for the defect-resilient embedded memory system for multimedia SOCs. Existing approach to build defect map of embedded memories is based on the CAM (Content Addressable Memory) organization. But, it consumes too much power and relatively large chip area. It may be serious problem in the near future for very deep submicron technologies. Therefore, we propose the SRAM-based defect map organization to reduce both the power consumption and chip area. We also develop new defect map access algorithm to minimize the number of defect map access operations to save power. Our estimation results show the new scheme based on SRAM defect map organization consumes only 1/4 times of power at BER=1.0% compared with the power overhead by the existing approach. © Springer-Verlag Berlin Heidelberg 2007.

AB - In this paper, we propose the low power and low area defect map organization for the defect-resilient embedded memory system for multimedia SOCs. Existing approach to build defect map of embedded memories is based on the CAM (Content Addressable Memory) organization. But, it consumes too much power and relatively large chip area. It may be serious problem in the near future for very deep submicron technologies. Therefore, we propose the SRAM-based defect map organization to reduce both the power consumption and chip area. We also develop new defect map access algorithm to minimize the number of defect map access operations to save power. Our estimation results show the new scheme based on SRAM defect map organization consumes only 1/4 times of power at BER=1.0% compared with the power overhead by the existing approach. © Springer-Verlag Berlin Heidelberg 2007.

UR - http://www.scopus.com/inward/record.url?scp=38049090289&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783540743088

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

ER -

An alternative organization of defect map for defect-resilient embedded on-chip memories

Abstract

Bibliographical note

Other files and links

Fingerprint

Cite this