TY - JOUR
T1 - Amorphous silicon oxide window layers for high-efficiency silicon heterojunction solar cells
AU - Peter Seif, Johannes
AU - Descoeudres, Antoine
AU - Filipič, Miha
AU - Smole, Franc
AU - Topič, Marko
AU - Charles Holman, Zachary
AU - De Wolf, Stefaan
AU - Ballif, Christophe
PY - 2014/1/14
Y1 - 2014/1/14
N2 - In amorphous/crystalline silicon heterojunction solar cells, optical losses can be mitigated by replacing the amorphous silicon films by wider bandgap amorphous silicon oxide layers. In this article, we use stacks of intrinsic amorphous silicon and amorphous silicon oxide as front intrinsic buffer layers and show that this increases the short-circuit current density by up to 0.43 mA/cm2 due to less reflection and a higher transparency at short wavelengths. Additionally, high open-circuit voltages can be maintained, thanks to good interface passivation. However, we find that the gain in current is more than offset by losses in fill factor. Aided by device simulations, we link these losses to impeded carrier collection fundamentally caused by the increased valence band offset at the amorphous/crystalline interface. Despite this, carrier extraction can be improved by raising the temperature; we find that cells with amorphous silicon oxide window layers show an even lower temperature coefficient than reference heterojunction solar cells (-0.1/°C relative drop in efficiency, compared to -0.3/°C). Hence, even though cells with oxide layers do not outperform cells with the standard design at room temperature, at higher temperatures-which are closer to the real working conditions encountered in the field-they show superior performance in both experiment and simulation.
AB - In amorphous/crystalline silicon heterojunction solar cells, optical losses can be mitigated by replacing the amorphous silicon films by wider bandgap amorphous silicon oxide layers. In this article, we use stacks of intrinsic amorphous silicon and amorphous silicon oxide as front intrinsic buffer layers and show that this increases the short-circuit current density by up to 0.43 mA/cm2 due to less reflection and a higher transparency at short wavelengths. Additionally, high open-circuit voltages can be maintained, thanks to good interface passivation. However, we find that the gain in current is more than offset by losses in fill factor. Aided by device simulations, we link these losses to impeded carrier collection fundamentally caused by the increased valence band offset at the amorphous/crystalline interface. Despite this, carrier extraction can be improved by raising the temperature; we find that cells with amorphous silicon oxide window layers show an even lower temperature coefficient than reference heterojunction solar cells (-0.1/°C relative drop in efficiency, compared to -0.3/°C). Hence, even though cells with oxide layers do not outperform cells with the standard design at room temperature, at higher temperatures-which are closer to the real working conditions encountered in the field-they show superior performance in both experiment and simulation.
UR - http://www.scopus.com/inward/record.url?scp=84892402599&partnerID=8YFLogxK
U2 - 10.1063/1.4861404
DO - 10.1063/1.4861404
M3 - Article
AN - SCOPUS:84892402599
SN - 0021-8979
VL - 115
JO - Journal of Applied Physics
JF - Journal of Applied Physics
IS - 2
M1 - 024502
ER -