Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

C. S. Park; M. M. Hussain; K. Tateiw; J. Huang; J. Lin; T. Ngai; S. Lian; K. Rader; B. Taylor; P. D. Kirsch; R. Jammy

doi:10.1109/VTSA.2010.5488940

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

C. S. Park, M. M. Hussain, K. Tateiw, J. Huang, J. Lin, T. Ngai, S. Lian, K. Rader, B. Taylor, P. D. Kirsch, R. Jammy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS V_fb and high pMOS V_fb (ΔEWF=∼900mV) without the V_fb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 μA/μm at 1nA/μm for V_dd=1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced R_ext,[iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.

Original language	English (US)
Title of host publication	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages	80-81
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2010.5488940
State	Published - 2010
Event	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China Duration: Apr 26 2010 → Apr 28 2010

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Other

Other	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Country/Territory	Taiwan, Province of China
City	Hsin Chu
Period	04/26/10 → 04/28/10

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture

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10.1109/VTSA.2010.5488940

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Park, C. S., Hussain, M. M., Tateiw, K., Huang, J., Lin, J., Ngai, T., Lian, S., Rader, K., Taylor, B., Kirsch, P. D., & Jammy, R. (2010). Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 (pp. 80-81). Article 5488940 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). https://doi.org/10.1109/VTSA.2010.5488940

Park, C. S. ; Hussain, M. M. ; Tateiw, K. et al. / Alternative approaches for high-k/metal gate CMOS : Low temperature process (gate last) and SiGe channel. Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. pp. 80-81 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010).

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title = "Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel",

abstract = "A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS Vfb (ΔEWF=∼900mV) without the Vfb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 μA/μm at 1nA/μm for Vdd=1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced Rext,[iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.",

author = "Park, {C. S.} and Hussain, {M. M.} and K. Tateiw and J. Huang and J. Lin and T. Ngai and S. Lian and K. Rader and B. Taylor and Kirsch, {P. D.} and R. Jammy",

year = "2010",

doi = "10.1109/VTSA.2010.5488940",

language = "English (US)",

isbn = "9781424450633",

series = "Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010",

pages = "80--81",

booktitle = "Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010",

note = "2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 ; Conference date: 26-04-2010 Through 28-04-2010",

}

Park, CS, Hussain, MM, Tateiw, K, Huang, J, Lin, J, Ngai, T, Lian, S, Rader, K, Taylor, B, Kirsch, PD & Jammy, R 2010, Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel. in Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010., 5488940, Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, pp. 80-81, 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, Hsin Chu, Taiwan, Province of China, 04/26/10. https://doi.org/10.1109/VTSA.2010.5488940

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel. / Park, C. S.; Hussain, M. M.; Tateiw, K. et al.
Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 80-81 5488940 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Park, C. S.

AU - Hussain, M. M.

AU - Tateiw, K.

AU - Huang, J.

AU - Lin, J.

AU - Ngai, T.

AU - Lian, S.

AU - Rader, K.

AU - Taylor, B.

AU - Kirsch, P. D.

AU - Jammy, R.

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N2 - A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS Vfb (ΔEWF=∼900mV) without the Vfb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 μA/μm at 1nA/μm for Vdd=1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced Rext,[iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.

AB - A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS Vfb (ΔEWF=∼900mV) without the Vfb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 μA/μm at 1nA/μm for Vdd=1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced Rext,[iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.

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T3 - Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

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BT - Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

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ER -

Park CS, Hussain MM, Tateiw K, Huang J, Lin J, Ngai T et al. Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 80-81. 5488940. (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). doi: 10.1109/VTSA.2010.5488940

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

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