Adaptive SRAM design for dynamic voltage scaling VLSI systems

In this paper, we present an adaptive eight-transistor SRAM design that is capable of extending the operation of SRAM cells in the subthreshold region as well as maintaining high performance at the nominal supply voltages. The effective PMOS transistor size is dynamically adjusted according to the value of the supply voltage in order to sustain a balanced voltage transfer characteristics over the range of supply voltage operation. Simulation results demonstrate a power saving of up to 25% using our adaptive SRAM cell designed to maintain acceptable static noise margins under supply voltage in the range of 0.2V to 1.2V . The adaptive SRAM is very efficient for VLSI systems working under dynamic voltage scaling schemes, where the system is required to function at a variable supply voltage that extends to the subthreshold region of operation. ©2007 IEEE.