Accurate loop self inductance bound for efficient inductance screening

Mosin Mondal; Yehia Massoud

doi:10.1109/TVLSI.2006.887837

Accurate loop self inductance bound for efficient inductance screening

Mosin Mondal, Yehia Massoud

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation. © 2006 IEEE.

Original language	English (US)
Pages (from-to)	1393-1397
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	14
Issue number	12
DOIs	https://doi.org/10.1109/TVLSI.2006.887837
State	Published - Dec 1 2006
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2022-09-13

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1109/TVLSI.2006.887837

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@article{91aa573f60f1474b82e1d7c6b01f859a,

title = "Accurate loop self inductance bound for efficient inductance screening",

abstract = "An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation. {\textcopyright} 2006 IEEE.",

author = "Mosin Mondal and Yehia Massoud",

note = "Generated from Scopus record by KAUST IRTS on 2022-09-13",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/TVLSI.2006.887837",

language = "English (US)",

volume = "14",

pages = "1393--1397",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - Accurate loop self inductance bound for efficient inductance screening

AU - Mondal, Mosin

AU - Massoud, Yehia

N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13

PY - 2006/12/1

Y1 - 2006/12/1

N2 - An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation. © 2006 IEEE.

AB - An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation. © 2006 IEEE.

UR - http://ieeexplore.ieee.org/document/4052350/

UR - http://www.scopus.com/inward/record.url?scp=33846620558&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2006.887837

DO - 10.1109/TVLSI.2006.887837

M3 - Article

SN - 1063-8210

VL - 14

SP - 1393

EP - 1397

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 12

ER -

Accurate loop self inductance bound for efficient inductance screening

Abstract

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