Accurate loop self inductance bound for efficient inductance screening

Mosin Mondal, Yehia Massoud

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation. © 2006 IEEE.
Original languageEnglish (US)
Pages (from-to)1393-1397
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number12
StatePublished - Dec 1 2006
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering


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