TY - GEN
T1 - Accurate analytical delay modeling of CMOS clock buffers considering power supply variations
AU - Kirolos, Sami
AU - Massoud, Yehia
AU - Ismail, Yehea
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2008/9/19
Y1 - 2008/9/19
N2 - In this paper, we present an accurate method for analytical derivation of CMOS clock buffers delay under power supply variations. The method involves modeling of the pull-up and pull-down resistances using approximated drain saturation current device equations for the buffers together with lumped resistive capacitive elements for the interconnects. Compared to circuit simulation results, the analytical model provides more than four orders of magnitude speedup while maintaining an average error of 0.26% with 3.0% standard deviation over the entire range of power supply and circuit parameters variations, making it suitable for timing analysis and optimization. ©2008 IEEE.
AB - In this paper, we present an accurate method for analytical derivation of CMOS clock buffers delay under power supply variations. The method involves modeling of the pull-up and pull-down resistances using approximated drain saturation current device equations for the buffers together with lumped resistive capacitive elements for the interconnects. Compared to circuit simulation results, the analytical model provides more than four orders of magnitude speedup while maintaining an average error of 0.26% with 3.0% standard deviation over the entire range of power supply and circuit parameters variations, making it suitable for timing analysis and optimization. ©2008 IEEE.
UR - http://ieeexplore.ieee.org/document/4542187/
UR - http://www.scopus.com/inward/record.url?scp=51749105610&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4542187
DO - 10.1109/ISCAS.2008.4542187
M3 - Conference contribution
SN - 9781424416844
SP - 3394
EP - 3397
BT - Proceedings - IEEE International Symposium on Circuits and Systems
ER -