A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

C. S. Park; Muhammad Mustafa Hussain; J. Huang; C. Park; K. Tateiwa; C. Young; H. K. Park; M. Cruz; D. Gilmer; K. Rader; J. Price; P. Lysaght; D. Heh; G. Bersuker; P. D. Kirsch; H. H. Tseng; R. Jammy

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

C. S. Park, Muhammad Mustafa Hussain, J. Huang, C. Park, K. Tateiwa^*, C. Young, H. K. Park, M. Cruz, D. Gilmer, K. Rader, J. Price, P. Lysaght, D. Heh, G. Bersuker, P. D. Kirsch, H. H. Tseng, R. Jammy

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32nm LSTP applications: V _t <±0.45V (at L _g =60nm) at EOT≤1.4nm, with 10 ⁵ × J _g reduction compared to SiO ₂ . This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO _x / AlO _x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

Original language	English (US)
Title of host publication	2009 Symposium on VLSI Technology, VLSIT 2009
Pages	208-209
Number of pages	2
State	Published - Nov 16 2009
Externally published	Yes
Event	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan Duration: Jun 16 2009 → Jun 18 2009

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
Country/Territory	Japan
City	Kyoto
Period	06/16/09 → 06/18/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Park, C. S., Hussain, M. M., Huang, J., Park, C., Tateiwa, K., Young, C., Park, H. K., Cruz, M., Gilmer, D., Rader, K., Price, J., Lysaght, P., Heh, D., Bersuker, G., Kirsch, P. D., Tseng, H. H., & Jammy, R. (2009). A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 208-209). [5200601] (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{7c0be9009c8045f0bb64781671042ce7,

title = "A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications",

abstract = " This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32nm LSTP applications: V t <±0.45V (at L g =60nm) at EOT≤1.4nm, with 10 5 × J g reduction compared to SiO 2 . This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO x / AlO x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets. ",

author = "Park, {C. S.} and Hussain, {Muhammad Mustafa} and J. Huang and C. Park and K. Tateiwa and C. Young and Park, {H. K.} and M. Cruz and D. Gilmer and K. Rader and J. Price and P. Lysaght and D. Heh and G. Bersuker and Kirsch, {P. D.} and Tseng, {H. H.} and R. Jammy",

year = "2009",

month = nov,

day = "16",

language = "English (US)",

isbn = "9784863480094",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "208--209",

booktitle = "2009 Symposium on VLSI Technology, VLSIT 2009",

note = "2009 Symposium on VLSI Technology, VLSIT 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

Park, CS, Hussain, MM, Huang, J, Park, C, Tateiwa, K, Young, C, Park, HK, Cruz, M, Gilmer, D, Rader, K, Price, J, Lysaght, P, Heh, D, Bersuker, G, Kirsch, PD, Tseng, HH & Jammy, R 2009, A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications. in 2009 Symposium on VLSI Technology, VLSIT 2009., 5200601, Digest of Technical Papers - Symposium on VLSI Technology, pp. 208-209, 2009 Symposium on VLSI Technology, VLSIT 2009, Kyoto, Japan, 06/16/09.

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications. / Park, C. S.; Hussain, Muhammad Mustafa; Huang, J. et al.
2009 Symposium on VLSI Technology, VLSIT 2009. 2009. p. 208-209 5200601 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

AU - Park, C. S.

AU - Hussain, Muhammad Mustafa

AU - Huang, J.

AU - Park, C.

AU - Tateiwa, K.

AU - Young, C.

AU - Park, H. K.

AU - Cruz, M.

AU - Gilmer, D.

AU - Rader, K.

AU - Price, J.

AU - Lysaght, P.

AU - Heh, D.

AU - Bersuker, G.

AU - Kirsch, P. D.

AU - Tseng, H. H.

AU - Jammy, R.

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AB - This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32nm LSTP applications: V t <±0.45V (at L g =60nm) at EOT≤1.4nm, with 10 5 × J g reduction compared to SiO 2 . This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO x / AlO x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

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BT - 2009 Symposium on VLSI Technology, VLSIT 2009

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Y2 - 16 June 2009 through 18 June 2009

ER -

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

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