A Precision, Energy-Efficient, Oversampling, Noise-Shaping Differential SAR Capacitance-to-Digital Converter

Abdulaziz Alhoshany*, Khaled N. Salama

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Scopus citations


This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the charge-redistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18- \mu \text{m} CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74-ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 \mu \text{W} from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step.

Original languageEnglish (US)
Article number8395284
Pages (from-to)392-401
Number of pages10
JournalIEEE Transactions on Instrumentation and Measurement
Issue number2
StatePublished - Feb 2019

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.


  • CMOS
  • Capacitance-to-digital converter (CDC)
  • capacitive sensor interface circuit
  • energy efficient
  • high-precision capacitive resolution
  • successive approximation (SAR)

ASJC Scopus subject areas

  • Instrumentation
  • Electrical and Electronic Engineering


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