A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities

Carmine Paolino, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


In this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.
Original languageEnglish (US)
Title of host publicationPRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781728135496
StatePublished - Jul 1 2019
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-02-15


Dive into the research topics of 'A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities'. Together they form a unique fingerprint.

Cite this