A novel low temperature integration of hybrid CMOS devices on flexible substrates

S. Gowrisanker; M. A. Quevedo-Lopez; H. N. Alshareef; B. E. Gnade; S. Venugopal; R. Krishna; K. Kaftanoglu; D. R. Allee

doi:10.1016/j.orgel.2009.06.012

A novel low temperature integration of hybrid CMOS devices on flexible substrates

S. Gowrisanker, M. A. Quevedo-Lopez^*, H. N. Alshareef, B. E. Gnade, S. Venugopal, R. Krishna, K. Kaftanoglu, D. R. Allee

^*Corresponding author for this work

Physical Sciences and Engineering

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.

Original language	English (US)
Pages (from-to)	1217-1222
Number of pages	6
Journal	Organic Electronics
Volume	10
Issue number	7
DOIs	https://doi.org/10.1016/j.orgel.2009.06.012
State	Published - Nov 2009

Keywords

Flexible electronics
Hybrid CMOS
NAND gate
NOR gate

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Biomaterials
General Chemistry
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

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10.1016/j.orgel.2009.06.012

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title = "A novel low temperature integration of hybrid CMOS devices on flexible substrates",

abstract = "In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.",

keywords = "Flexible electronics, Hybrid CMOS, NAND gate, NOR gate",

author = "S. Gowrisanker and Quevedo-Lopez, {M. A.} and Alshareef, {H. N.} and Gnade, {B. E.} and S. Venugopal and R. Krishna and K. Kaftanoglu and Allee, {D. R.}",

year = "2009",

month = nov,

doi = "10.1016/j.orgel.2009.06.012",

language = "English (US)",

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T1 - A novel low temperature integration of hybrid CMOS devices on flexible substrates

AU - Gowrisanker, S.

AU - Quevedo-Lopez, M. A.

AU - Alshareef, H. N.

AU - Gnade, B. E.

AU - Venugopal, S.

AU - Krishna, R.

AU - Kaftanoglu, K.

AU - Allee, D. R.

PY - 2009/11

Y1 - 2009/11

N2 - In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.

AB - In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/V s, respectively. Threshold voltages (Vt) are 1.14 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.

KW - Flexible electronics

KW - Hybrid CMOS

KW - NAND gate

KW - NOR gate

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DO - 10.1016/j.orgel.2009.06.012

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JO - Organic Electronics

JF - Organic Electronics

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ER -

A novel low temperature integration of hybrid CMOS devices on flexible substrates

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Keywords

ASJC Scopus subject areas

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