TY - GEN
T1 - A novel approach for K-best MIMO detection and its VLSI implementation
AU - Mondal, Sudip
AU - Salama, Khaled N.
AU - Ali, Warsame H.
PY - 2008
Y1 - 2008
N2 - Since the complexity of MIMO detection algorithms is exponential, the K-best algorithm is often chosen for efficient VLSI implementation. This detection problem is often viewed as a tree search problem where the Breadth First Search (BFS) method is adopted and only the K-best branches are kept at each level of the tree. An earlier VLSI implementation of the K-best BFS has been reported, however it has an inherent speed bottleneck due to the calculation of many path metrics and then sorting among them to select the K-best. In this paper an alternative implementation of the BFS is presented, which is suitable for VLSI implementation. To test the performance of this approach it has been applied to a 4X4 MIMO detector with a 64 QAM constellation. The results show less than 1dB degradation from the sphere decoding algorithm. The implementation of a single spiral cell, the basic block behind the system, occupies a 764μm2 of area and consumes a 52.58μw of power a 0.13μm CMOS technology.
AB - Since the complexity of MIMO detection algorithms is exponential, the K-best algorithm is often chosen for efficient VLSI implementation. This detection problem is often viewed as a tree search problem where the Breadth First Search (BFS) method is adopted and only the K-best branches are kept at each level of the tree. An earlier VLSI implementation of the K-best BFS has been reported, however it has an inherent speed bottleneck due to the calculation of many path metrics and then sorting among them to select the K-best. In this paper an alternative implementation of the BFS is presented, which is suitable for VLSI implementation. To test the performance of this approach it has been applied to a 4X4 MIMO detector with a 64 QAM constellation. The results show less than 1dB degradation from the sphere decoding algorithm. The implementation of a single spiral cell, the basic block behind the system, occupies a 764μm2 of area and consumes a 52.58μw of power a 0.13μm CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=51749097330&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4541573
DO - 10.1109/ISCAS.2008.4541573
M3 - Conference contribution
AN - SCOPUS:51749097330
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 936
EP - 939
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -