In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%. © World Scientific Publishing Company.
Bibliographical noteGenerated from Scopus record by KAUST IRTS on 2022-09-13
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering