In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - IEEE International Symposium on Circuits and Systems|
|Number of pages||4|
|State||Published - Dec 1 2005|