A low-power digital frequency divider for system-on-a-chip applications

Hesham Omran; Khaled M W Sharaf; Magdi Marzouk Ibrahim

doi:10.1109/MWSCAS.2011.6026674

A low-power digital frequency divider for system-on-a-chip applications

Hesham Omran, Khaled M W Sharaf, Magdi Marzouk Ibrahim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.

Original language	English (US)
Title of host publication	2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Print)	9781612848570
DOIs	https://doi.org/10.1109/MWSCAS.2011.6026674
State	Published - Aug 2011

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10.1109/MWSCAS.2011.6026674

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@inproceedings{4481b41aa7f8426d8d060c0566b905cc,

title = "A low-power digital frequency divider for system-on-a-chip applications",

abstract = "In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. {\textcopyright} 2011 IEEE.",

author = "Hesham Omran and Sharaf, {Khaled M W} and Ibrahim, {Magdi Marzouk}",

note = "KAUST Repository Item: Exported on 2020-10-01",

year = "2011",

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doi = "10.1109/MWSCAS.2011.6026674",

language = "English (US)",

isbn = "9781612848570",

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AU - Omran, Hesham

AU - Sharaf, Khaled M W

AU - Ibrahim, Magdi Marzouk

N1 - KAUST Repository Item: Exported on 2020-10-01

PY - 2011/8

Y1 - 2011/8

N2 - In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.

AB - In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.

UR - http://hdl.handle.net/10754/564406

UR - http://ieeexplore.ieee.org/document/6026674/

UR - http://www.scopus.com/inward/record.url?scp=80053650628&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2011.6026674

DO - 10.1109/MWSCAS.2011.6026674

M3 - Conference contribution

SN - 9781612848570

BT - 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

A low-power digital frequency divider for system-on-a-chip applications

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