TY - GEN
T1 - A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities
AU - Tarighat, Alireza
AU - Grayver, Eugene
AU - Eltawil, Ahmed
AU - Frigon, Jean Francois
AU - Poberezhskiy, Gennadiy
AU - Zou, Hanli
AU - Daneshrad, Babak
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2005/12/1
Y1 - 2005/12/1
N2 - An ASIC implementation of a WCDMA mobile terminal with 2-dimensional adaptive antenna-rake combining is presented in this paper. System analysis shows that adaptive antenna-rake combining techniques can significantly enhance the performance and capacity of cellular systems compared to conventional CDMA systems. A hardware efficient receiver architecture is implemented supporting both maximal ratio combing (MRC) and least mean squares (LMS) algorithm. Moreover, the proposed architectures allows for a dynamic and flexible allocation of available processing resources (total of 20 fingers) to different antennas and multipaths based on the instantaneous channel profile. The presented receiver can operate in both normal and space time transmit diversity (STTD) modes. The system was implemented in a 0.18μm CMOS process and the improvement was validated through real-time field trials. © 2005 IEEE.
AB - An ASIC implementation of a WCDMA mobile terminal with 2-dimensional adaptive antenna-rake combining is presented in this paper. System analysis shows that adaptive antenna-rake combining techniques can significantly enhance the performance and capacity of cellular systems compared to conventional CDMA systems. A hardware efficient receiver architecture is implemented supporting both maximal ratio combing (MRC) and least mean squares (LMS) algorithm. Moreover, the proposed architectures allows for a dynamic and flexible allocation of available processing resources (total of 20 fingers) to different antennas and multipaths based on the instantaneous channel profile. The presented receiver can operate in both normal and space time transmit diversity (STTD) modes. The system was implemented in a 0.18μm CMOS process and the improvement was validated through real-time field trials. © 2005 IEEE.
UR - http://ieeexplore.ieee.org/document/1568610/
UR - http://www.scopus.com/inward/record.url?scp=33847093883&partnerID=8YFLogxK
U2 - 10.1109/CICC.2005.1568610
DO - 10.1109/CICC.2005.1568610
M3 - Conference contribution
SN - 0780390237
BT - Proceedings of the Custom Integrated Circuits Conference
ER -