A low-power 802.11 AD compatible 60-GHz phase-locked loop in 65-NM CMOS

Engineering

• Feedback Loop 100%
• Charge Pump 50%
• Capacitance 50%
• Electric Power Distribution 50%
• Integrated System 50%
• System-on-Chip 50%
• Mixers (Machinery) 50%
• Frequency Band 50%
• Passive Filters 50%
• Optimization Approach 50%
• Design Procedure 50%
• Dead Zone 50%
• Fundamental Frequency 50%
• Phase Noise 50%
• Local Oscillator 50%
• Phase Margin 50%
• Frequency Division 50%
• Stages 50%
• Chains 50%
• Reduction 50%
• Coverage 50%
• Antenna 50%
• Transmitter 50%
• Capacitive Loading 50%
• Prescaler 50%
• Voltage-Controlled Oscillator 50%
• Silicon 50%