A high speed open source controller for FPGA partial reconfiguration

Kizheppatt Vipin; Suhaib A. Fahmy

doi:10.1109/FPT.2012.6412113

A high speed open source controller for FPGA partial reconfiguration

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

46 Scopus citations

Abstract

Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community. © 2012 IEEE.

Original language	English (US)
Title of host publication	FPT 2012 - 2012 International Conference on Field-Programmable Technology
Pages	61-66
Number of pages	6
DOIs	https://doi.org/10.1109/FPT.2012.6412113
State	Published - Dec 1 2012
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2021-03-16

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10.1109/FPT.2012.6412113

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title = "A high speed open source controller for FPGA partial reconfiguration",

abstract = "Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community. {\textcopyright} 2012 IEEE.",

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N2 - Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community. © 2012 IEEE.

AB - Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community. © 2012 IEEE.

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SN - 9781467328449

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EP - 66

BT - FPT 2012 - 2012 International Conference on Field-Programmable Technology

ER -

A high speed open source controller for FPGA partial reconfiguration

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