A High Speed Dynamic StrongARM Latch Comparator

Mohammed Al-Qadasi, Abdullah Alshehri, Abdullah Saud Mohammed Almansouri, Talal Al Attar, Hossein Fariborzi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.
Original languageEnglish (US)
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages2
ISBN (Print)9781538673928
StatePublished - Feb 28 2019

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01


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