A fully differential monolithic LNA with on-chip antenna for a short range wireless receiver

Muhammad Arsalan; Atif Shamim; Langis Roy; Maitham Shams

doi:10.1109/LMWC.2009.2029760

A fully differential monolithic LNA with on-chip antenna for a short range wireless receiver

Muhammad Arsalan^*, Atif Shamim, Langis Roy, Maitham Shams

^*Corresponding author for this work

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20 Scopus citations

Abstract

This letter presents the smallest reported 5 GHz receiver chip (1.3 mm ²) with an on-chip antenna in standard 0.13 μm CMOS process. The miniaturization is achieved by placing the circuits inside a meandered antenna. The on-chip antenna is conjugately matched to the low noise amplifier (LNA) over a wide frequency range. The design methodology for co-design of the on-chip antenna and LNA is described. The LNA is completely differential, consumes only 8 mW of power and provides a gain of 21 dB. Design tradeoffs and measurement challenges are given.

Original language	English (US)
Article number	5234040
Pages (from-to)	674-676
Number of pages	3
Journal	IEEE Microwave and Wireless Components Letters
Volume	19
Issue number	10
DOIs	https://doi.org/10.1109/LMWC.2009.2029760
State	Published - Oct 2009

Keywords

Low noise amplifier (LNA)
On-chip antenna
Receiver

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/LMWC.2009.2029760

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AU - Shams, Maitham

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N2 - This letter presents the smallest reported 5 GHz receiver chip (1.3 mm 2) with an on-chip antenna in standard 0.13 μm CMOS process. The miniaturization is achieved by placing the circuits inside a meandered antenna. The on-chip antenna is conjugately matched to the low noise amplifier (LNA) over a wide frequency range. The design methodology for co-design of the on-chip antenna and LNA is described. The LNA is completely differential, consumes only 8 mW of power and provides a gain of 21 dB. Design tradeoffs and measurement challenges are given.

AB - This letter presents the smallest reported 5 GHz receiver chip (1.3 mm 2) with an on-chip antenna in standard 0.13 μm CMOS process. The miniaturization is achieved by placing the circuits inside a meandered antenna. The on-chip antenna is conjugately matched to the low noise amplifier (LNA) over a wide frequency range. The design methodology for co-design of the on-chip antenna and LNA is described. The LNA is completely differential, consumes only 8 mW of power and provides a gain of 21 dB. Design tradeoffs and measurement challenges are given.

KW - Low noise amplifier (LNA)

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ER -

A fully differential monolithic LNA with on-chip antenna for a short range wireless receiver

Abstract

Keywords

ASJC Scopus subject areas

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