A fault-aware dynamic routing algorithm for on-chip networks

Amir Hosseini, Tamer Ragheb, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

59 Scopus citations


Given the spatial and temporal randomness of soft and permanent errors in the state-of-the-art system-on-chips (SoCs), dynamic routing algorithms that can adapt themselves accordingly are highly required for network-on-chip (NoC) applications. In this paper, we present a new dynamic routing algorithm for NoC applications that has the ability to locate and deal with both static and dynamic permanent failures and distinguish them from soft errors. In addition, our presented algorithm has the advantage of distributing the load over the whole network by considering the stress factors. Simulation results demonstrate the advantage of our routing algorithm in terms of functionality, latency, and energy consumption compared to directed flooding based fault tolerant routing algorithms in the presence of both soft errors and permanent faults. Our algorithm can achieves 1.95x less latency and consumes 3.15x less energy consumption on average. ©2008 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Number of pages4
StatePublished - Sep 19 2008
Externally publishedYes

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