TY - GEN
T1 - A fast chaos-based true random number generator for cryptographic applications
AU - Pareschi, Fabio
AU - Setti, Gianluca
AU - Rovatti, Riccardo
N1 - Generated from Scopus record by KAUST IRTS on 2023-02-15
PY - 2006/12/1
Y1 - 2006/12/1
N2 - We present the design and the validation by means of state-of-the-art randomness tests of a high-quality true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of interleaved chaotic maps. Developing the circuit design relying on pipeline A/D technology, which is ubiquity used in all mixed signal systems, allow us to design a fast and very reliable TRNG. A prototype has been implemented in AMS 0.35 μm 2P3M technology and has a nominal throughput of 40 Mbits per second. The active area occupied by the chip is about 0.52 mm 2 and the power consumption is less than 30 mW. © 2006 IEEE.
AB - We present the design and the validation by means of state-of-the-art randomness tests of a high-quality true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of interleaved chaotic maps. Developing the circuit design relying on pipeline A/D technology, which is ubiquity used in all mixed signal systems, allow us to design a fast and very reliable TRNG. A prototype has been implemented in AMS 0.35 μm 2P3M technology and has a nominal throughput of 40 Mbits per second. The active area occupied by the chip is about 0.52 mm 2 and the power consumption is less than 30 mW. © 2006 IEEE.
UR - https://ieeexplore.ieee.org/document/4099721/
UR - http://www.scopus.com/inward/record.url?scp=84865424156&partnerID=8YFLogxK
U2 - 10.1109/ESSCIR.2006.307548
DO - 10.1109/ESSCIR.2006.307548
M3 - Conference contribution
SN - 1424403022
SP - 130
EP - 133
BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
ER -