A fast chaos-based true random number generator for cryptographic applications

Fabio Pareschi, Gianluca Setti, Riccardo Rovatti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

71 Scopus citations


We present the design and the validation by means of state-of-the-art randomness tests of a high-quality true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of interleaved chaotic maps. Developing the circuit design relying on pipeline A/D technology, which is ubiquity used in all mixed signal systems, allow us to design a fast and very reliable TRNG. A prototype has been implemented in AMS 0.35 μm 2P3M technology and has a nominal throughput of 40 Mbits per second. The active area occupied by the chip is about 0.52 mm 2 and the power consumption is less than 30 mW. © 2006 IEEE.
Original languageEnglish (US)
Title of host publicationESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Number of pages4
StatePublished - Dec 1 2006
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-02-15


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