A design of 44.1 fj/conv-step 12-bit 80 ms/s time interleaved hybrid type sar adc with redundancy capacitor and on-chip time-skew calibration
Deeksha Verma, Behnam S. Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, Younggun Pu, Sang Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang Yoon Lee
Research output: Contribution to journal › Article › peer-review
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