A combined channel and hardware noise resilient Viterbi decoder

Amr M.A. Hussien; Muhammed S. Khairy; Amin Khajeh; Kiarash Amiri; Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/ACSSC.2010.5757543

A combined channel and hardware noise resilient Viterbi decoder

Amr M.A. Hussien, Muhammed S. Khairy, Amin Khajeh, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Scopus citations

Abstract

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library. © 2010 IEEE.

Original language	English (US)
Title of host publication	Conference Record - Asilomar Conference on Signals, Systems and Computers
DOIs	https://doi.org/10.1109/ACSSC.2010.5757543
State	Published - Dec 1 2010
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2019-11-20

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@inproceedings{96b127959ab649bba64e54b63c308d17,

title = "A combined channel and hardware noise resilient Viterbi decoder",

abstract = "Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library. {\textcopyright} 2010 IEEE.",

author = "Hussien, {Amr M.A.} and Khairy, {Muhammed S.} and Amin Khajeh and Kiarash Amiri and Eltawil, {Ahmed M.} and Kurdahi, {Fadi J.}",

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year = "2010",

month = dec,

day = "1",

doi = "10.1109/ACSSC.2010.5757543",

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T1 - A combined channel and hardware noise resilient Viterbi decoder

AU - Hussien, Amr M.A.

AU - Khairy, Muhammed S.

AU - Khajeh, Amin

AU - Amiri, Kiarash

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi J.

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library. © 2010 IEEE.

AB - Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library. © 2010 IEEE.

UR - http://ieeexplore.ieee.org/document/5757543/

UR - http://www.scopus.com/inward/record.url?scp=79958011369&partnerID=8YFLogxK

U2 - 10.1109/ACSSC.2010.5757543

DO - 10.1109/ACSSC.2010.5757543

M3 - Conference contribution

SN - 9781424497218

BT - Conference Record - Asilomar Conference on Signals, Systems and Computers

ER -

A combined channel and hardware noise resilient Viterbi decoder

Abstract

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