A class of low power error compensation iterative decoders

Amr M.A. Hussien, Muhammad S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. © 2011 IEEE.
Original languageEnglish (US)
Title of host publicationGLOBECOM - IEEE Global Telecommunications Conference
StatePublished - Dec 1 2011
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2019-11-20


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