This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. © 2011 IEEE.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Aug 2012|
Bibliographical noteKAUST Repository Item: Exported on 2020-10-01
Acknowledgements: Manuscript received September 17, 2010; revised January 13, 2011 and April 14, 2011; accepted May 22, 2011. Date of publication July 18, 2011; date of current version June 14, 2012. This work was supported in part by the Department of Justice, National Institute of Justice DOJ/NIJ under grant 2006-IJ-CX-K044.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering