We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.
|Original language||English (US)|
|Title of host publication||2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|State||Published - Oct 6 2016|