A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Hesham Omran, Abdulaziz Alhoshany, Hamzah Alahmadi, Khaled N. Salama

Research output: Contribution to journalArticlepeer-review

54 Scopus citations


A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.
Original languageEnglish (US)
Pages (from-to)310-321
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number2
StatePublished - Nov 16 2016

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: The authors would like to thank the reviewers for their valuable and stimulating comments.


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