A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application

Abdullah Alshehri; Abdullah Alqarni; Kuilian Yang; Hossein Fariborzi

doi:10.1109/PRIME58259.2023.10161769

A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application

Abdullah Alshehri^*, Abdullah Alqarni, Kuilian Yang, Hossein Fariborzi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.

Original language	English (US)
Title of host publication	PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	365-368
Number of pages	4
ISBN (Electronic)	9798350303209
DOIs	https://doi.org/10.1109/PRIME58259.2023.10161769
State	Published - 2023
Event	18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 - Valencia, Spain Duration: Jun 18 2023 → Jun 21 2023

Publication series

Name	PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings

Conference

Conference	18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023
Country/Territory	Spain
City	Valencia
Period	06/18/23 → 06/21/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

cross-coupled transistors
Current Mode Logic (CML)
D-Latch
Forward body biasing
low power
MCML

ASJC Scopus subject areas

Artificial Intelligence
Software
Safety, Risk, Reliability and Quality
Modeling and Simulation

Access to Document

10.1109/PRIME58259.2023.10161769

Cite this

Alshehri, A., Alqarni, A., Yang, K., & Fariborzi, H. (2023). A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application. In PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings (pp. 365-368). (PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME58259.2023.10161769

Alshehri, Abdullah ; Alqarni, Abdullah ; Yang, Kuilian et al. / A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application. PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. pp. 365-368 (PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings).

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title = "A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application",

abstract = "In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.",

keywords = "cross-coupled transistors, Current Mode Logic (CML), D-Latch, Forward body biasing, low power, MCML",

author = "Abdullah Alshehri and Abdullah Alqarni and Kuilian Yang and Hossein Fariborzi",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 ; Conference date: 18-06-2023 Through 21-06-2023",

year = "2023",

doi = "10.1109/PRIME58259.2023.10161769",

language = "English (US)",

series = "PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings",

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Alshehri, A, Alqarni, A, Yang, K & Fariborzi, H 2023, A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application. in PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings. PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 365-368, 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023, Valencia, Spain, 06/18/23. https://doi.org/10.1109/PRIME58259.2023.10161769

A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application. / Alshehri, Abdullah; Alqarni, Abdullah; Yang, Kuilian et al.
PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. p. 365-368 (PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application

AU - Alshehri, Abdullah

AU - Alqarni, Abdullah

AU - Yang, Kuilian

AU - Fariborzi, Hossein

PY - 2023

Y1 - 2023

N2 - In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.

AB - In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.

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KW - Current Mode Logic (CML)

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KW - Forward body biasing

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Y2 - 18 June 2023 through 21 June 2023

ER -

Alshehri A, Alqarni A, Yang K, Fariborzi H. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application. In PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. p. 365-368. (PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings). doi: 10.1109/PRIME58259.2023.10161769

A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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