Abstract
In this paper, a new StrongARM latch comparator design has been proposed for low-power high-speed applications. The proposed design improves the energy consumption and propagation delay when compared to the previous designs in the literature. The proposed design is post-layout simulated in TSMC 65 nm technology node and it achieves a low energy consumption of 19.31 fJ per operation and a low propagation delay of 211 ps. Moreover, the proposed design shows a highly favorable input offset voltage of 0.56 mV and achieves a maximum frequency of 8 GHz. Furthermore, the proposed design reduced the transistor stack that allows it to be used in the low-voltage supply application.
| Original language | English (US) |
|---|---|
| Title of host publication | ISCAS 2024 - IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350330991 |
| DOIs | |
| State | Published - 2024 |
| Event | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: May 19 2024 → May 22 2024 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 |
|---|---|
| Country/Territory | Singapore |
| City | Singapore |
| Period | 05/19/24 → 05/22/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- CMOS latch
- forward body biasing
- high-speed circuit
- low-power circuit
- offset voltage
- StrongARM latch comparator
ASJC Scopus subject areas
- Electrical and Electronic Engineering
