A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture

Abdullah S. Almansouri; Abdullah Alturki; Hossein Fariborzi; Khaled N. Salama; Talal Al-Attar

doi:10.1109/PRIME.2018.8430349

A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture

Abdullah S. Almansouri, Abdullah Alturki, Hossein Fariborzi, Khaled N. Salama, Talal Al-Attar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.

Original language	English (US)
Title of host publication	PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	37-40
Number of pages	4
ISBN (Print)	9781538653869
DOIs	https://doi.org/10.1109/PRIME.2018.8430349
State	Published - Aug 8 2018
Event	14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 - Prague, Czech Republic Duration: Jul 2 2018 → Jul 5 2018

Publication series

Name	PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics

Conference

Conference	14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018
Country/Territory	Czech Republic
City	Prague
Period	07/2/18 → 07/5/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Comparator
Data converter
Flash ADC
Helpee StrongARM
StrongARM

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Instrumentation
Electrical and Electronic Engineering

Access to Document

10.1109/PRIME.2018.8430349

Cite this

Almansouri, A. S., Alturki, A., Fariborzi, H., Salama, K. N., & Al-Attar, T. (2018). A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. In PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics (pp. 37-40). Article 8430349 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2018.8430349

Almansouri, Abdullah S. ; Alturki, Abdullah ; Fariborzi, Hossein et al. / A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 37-40 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics).

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title = "A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture",

abstract = "This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.",

keywords = "Comparator, Data converter, Flash ADC, Helpee StrongARM, StrongARM",

author = "Almansouri, {Abdullah S.} and Abdullah Alturki and Hossein Fariborzi and Salama, {Khaled N.} and Talal Al-Attar",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 ; Conference date: 02-07-2018 Through 05-07-2018",

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Almansouri, AS, Alturki, A, Fariborzi, H, Salama, KN & Al-Attar, T 2018, A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. in PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics., 8430349, PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics, Institute of Electrical and Electronics Engineers Inc., pp. 37-40, 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018, Prague, Czech Republic, 07/2/18. https://doi.org/10.1109/PRIME.2018.8430349

A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. / Almansouri, Abdullah S.; Alturki, Abdullah; Fariborzi, Hossein et al.
PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc., 2018. p. 37-40 8430349 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Al-Attar, Talal

PY - 2018/8/8

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N2 - This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.

AB - This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.

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Almansouri AS, Alturki A, Fariborzi H, Salama KN , Al-Attar T. A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. In PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc. 2018. p. 37-40. 8430349. (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics). doi: 10.1109/PRIME.2018.8430349

A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this