Abstract
Device scaling has been implemented throughout the chip making industry as a means of increasing density and performance. This has imposed a lot of challenging tasks to develop new processes, improve process window and reduce defect density. In our fabrication of 65nm W contact to Ml scheme, we found severe metal 1 shorts after electrical testing, these shorts potentially causing drop in SRAM yield of ∼ 40%. It is interesting to note that Ml shorts are induced by W CMP process. Detailed investigation showed that Ml shorts are related to post-W CMP topography and high-density of contact, which trap W-residues. This has subsequently affected Ml patterning processes. Electrical testing result shows the dependency of Ml failure rate on contact pattern density. In addition, cross-section TEM micrograph shows that adjacent metal lines are connected by filament, which contained Cu by EDX measurement. Base on our hypothesis, we have proposed the best ways to suppress this issue by optimizing W CMP platen 3 polishing time and DI water buffing time.
Original language | English (US) |
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Pages | 117-122 |
Number of pages | 6 |
State | Published - 2007 |
Externally published | Yes |
Event | 12th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2007 - Fremont, CA, United States Duration: Mar 6 2007 → Mar 8 2007 |
Other
Other | 12th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2007 |
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Country/Territory | United States |
City | Fremont, CA |
Period | 03/6/07 → 03/8/07 |
Keywords
- Ml shorts and Contact Pattern Density
- W CMP
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering