3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

Ching Hua Wang; Connor McClellan; Yuanyuan Shi; Xin Zheng; Victoria Chen; Mario Lanza; Eric Pop; H. S. Philip Wong

doi:10.1109/IEDM.2018.8614495

3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

Ching Hua Wang, Connor McClellan, Yuanyuan Shi, Xin Zheng, Victoria Chen, Mario Lanza, Eric Pop, H. S. Philip Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

36 Scopus citations

Abstract

We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < 130 μA and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS 2 transistor has low off-current due to the large band gap of monolayer MoS 2 (E g > 2 eV). We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.

Original language	English (US)
Title of host publication	Technical Digest - International Electron Devices Meeting, IEDM
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	22.5.1-22.5.4
Number of pages	1
ISBN (Print)	9781728119878
DOIs	https://doi.org/10.1109/IEDM.2018.8614495
State	Published - Jan 16 2019
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2021-03-16

Access to Document

10.1109/IEDM.2018.8614495

Cite this

Wang, C. H., McClellan, C., Shi, Y., Zheng, X., Chen, V., Lanza, M., Pop, E., & Philip Wong, H. S. (2019). 3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature. In Technical Digest - International Electron Devices Meeting, IEDM (pp. 22.5.1-22.5.4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614495

@inproceedings{8be92a2e96c44d66ad4775c9f4769173,

title = "3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature",

abstract = "We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < 130 μA and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS 2 transistor has low off-current due to the large band gap of monolayer MoS 2 (E g > 2 eV). We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.",

author = "Wang, {Ching Hua} and Connor McClellan and Yuanyuan Shi and Xin Zheng and Victoria Chen and Mario Lanza and Eric Pop and {Philip Wong}, {H. S.}",

note = "Generated from Scopus record by KAUST IRTS on 2021-03-16",

year = "2019",

month = jan,

day = "16",

doi = "10.1109/IEDM.2018.8614495",

language = "English (US)",

isbn = "9781728119878",

pages = "22.5.1--22.5.4",

booktitle = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

Wang, CH, McClellan, C, Shi, Y, Zheng, X, Chen, V, Lanza, M, Pop, E & Philip Wong, HS 2019, 3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature. in Technical Digest - International Electron Devices Meeting, IEDM. Institute of Electrical and Electronics Engineers Inc., pp. 22.5.1-22.5.4. https://doi.org/10.1109/IEDM.2018.8614495

3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature. / Wang, Ching Hua; McClellan, Connor; Shi, Yuanyuan et al.
Technical Digest - International Electron Devices Meeting, IEDM. Institute of Electrical and Electronics Engineers Inc., 2019. p. 22.5.1-22.5.4.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - 3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

AU - Wang, Ching Hua

AU - McClellan, Connor

AU - Shi, Yuanyuan

AU - Zheng, Xin

AU - Chen, Victoria

AU - Lanza, Mario

AU - Pop, Eric

AU - Philip Wong, H. S.

N1 - Generated from Scopus record by KAUST IRTS on 2021-03-16

PY - 2019/1/16

Y1 - 2019/1/16

N2 - We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < 130 μA and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS 2 transistor has low off-current due to the large band gap of monolayer MoS 2 (E g > 2 eV). We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.

AB - We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < 130 μA and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS 2 transistor has low off-current due to the large band gap of monolayer MoS 2 (E g > 2 eV). We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.

UR - https://ieeexplore.ieee.org/document/8614495/

UR - http://www.scopus.com/inward/record.url?scp=85061807085&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2018.8614495

DO - 10.1109/IEDM.2018.8614495

M3 - Conference contribution

SN - 9781728119878

SP - 22.5.1-22.5.4

BT - Technical Digest - International Electron Devices Meeting, IEDM

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

Abstract

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this