2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices

Nazek El-Atab; Ayse Ozcan; Sabri Alkis; Ali K. Okyay; Ammar Nayfeh

doi:10.1109/NANO.2014.6968168

2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices

Nazek El-Atab, Ayse Ozcan, Sabri Alkis, Ali K. Okyay, Ammar Nayfeh

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (V_t) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages.

Original language	English (US)
Title of host publication	Proceedings of the IEEE Conference on Nanotechnology
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	505-509
Number of pages	5
ISBN (Electronic)	9781479956227
DOIs	https://doi.org/10.1109/NANO.2014.6968168
State	Published - Nov 26 2014
Event	2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014 - Toronto, Canada Duration: Aug 18 2014 → Aug 21 2014

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
ISSN (Electronic)	1944-9399

Conference

Conference	2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014
Country/Territory	Canada
City	Toronto
Period	08/18/14 → 08/21/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Modeling and Simulation
Instrumentation

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10.1109/NANO.2014.6968168

Cite this

El-Atab, N., Ozcan, A., Alkis, S., Okyay, A. K., & Nayfeh, A. (2014). 2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices. In Proceedings of the IEEE Conference on Nanotechnology (pp. 505-509). Article 6968168 (Proceedings of the IEEE Conference on Nanotechnology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NANO.2014.6968168

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abstract = "In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages.",

author = "Nazek El-Atab and Ayse Ozcan and Sabri Alkis and Okyay, {Ali K.} and Ammar Nayfeh",

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El-Atab, N, Ozcan, A, Alkis, S, Okyay, AK & Nayfeh, A 2014, 2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices. in Proceedings of the IEEE Conference on Nanotechnology., 6968168, Proceedings of the IEEE Conference on Nanotechnology, Institute of Electrical and Electronics Engineers Inc., pp. 505-509, 2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014, Toronto, Canada, 08/18/14. https://doi.org/10.1109/NANO.2014.6968168

2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices. / El-Atab, Nazek; Ozcan, Ayse; Alkis, Sabri et al.
Proceedings of the IEEE Conference on Nanotechnology. Institute of Electrical and Electronics Engineers Inc., 2014. p. 505-509 6968168 (Proceedings of the IEEE Conference on Nanotechnology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Nayfeh, Ammar

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N2 - In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages.

AB - In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages.

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2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices

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