1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan, Joris de Riet, Thijs Bel, Ilias Katsouras, Lukasz Witczak, Auke Jisk Kronemeijer, Rene A. J. Janssen, Gerwin H. Gelinck

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.
Original languageEnglish (US)
Pages (from-to)1217-1220
Number of pages4
JournalIEEE Electron Device Letters
Issue number8
StatePublished - Aug 2020
Externally publishedYes

Bibliographical note

KAUST Repository Item: Exported on 2021-02-11
Acknowledged KAUST grant number(s): OSR-CRG2018-3783
Acknowledgements: This work was supported in part by the European Regional Development Fund through the Flexlines Project through the Interreg V-Program Flanders-The Netherlands, a Cross-Border Cooperation Program, in part by the Province of Noord-Brabant, The Netherlands, and in part by the King Abdullah University of Science and Technology (KAUST) Office for Sponsored Research (OSR) under Award OSR-CRG2018-3783.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.


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