1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan; Joris de Riet; Thijs Bel; Ilias Katsouras; Lukasz Witczak; Auke Jisk Kronemeijer; Rene A. J. Janssen; Gerwin H. Gelinck

doi:10.1109/led.2020.3006343

1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan, Joris de Riet, Thijs Bel, Ilias Katsouras, Lukasz Witczak, Auke Jisk Kronemeijer, Rene A. J. Janssen, Gerwin H. Gelinck

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.

Original language	English (US)
Pages (from-to)	1217-1220
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	41
Issue number	8
DOIs	https://doi.org/10.1109/led.2020.3006343
State	Published - Aug 2020
Externally published	Yes

Bibliographical note

KAUST Repository Item: Exported on 2021-02-11
Acknowledged KAUST grant number(s): OSR-CRG2018-3783
Acknowledgements: This work was supported in part by the European Regional Development Fund through the Flexlines Project through the Interreg V-Program Flanders-The Netherlands, a Cross-Border Cooperation Program, in part by the Province of Noord-Brabant, The Netherlands, and in part by the King Abdullah University of Science and Technology (KAUST) Office for Sponsored Research (OSR) under Award OSR-CRG2018-3783.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.

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10.1109/led.2020.3006343

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title = "1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography",

abstract = "Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.",

author = "Tamer Dogan and {de Riet}, Joris and Thijs Bel and Ilias Katsouras and Lukasz Witczak and Kronemeijer, {Auke Jisk} and Janssen, {Rene A. J.} and Gelinck, {Gerwin H.}",

note = "KAUST Repository Item: Exported on 2021-02-11 Acknowledged KAUST grant number(s): OSR-CRG2018-3783 Acknowledgements: This work was supported in part by the European Regional Development Fund through the Flexlines Project through the Interreg V-Program Flanders-The Netherlands, a Cross-Border Cooperation Program, in part by the Province of Noord-Brabant, The Netherlands, and in part by the King Abdullah University of Science and Technology (KAUST) Office for Sponsored Research (OSR) under Award OSR-CRG2018-3783. This publication acknowledges KAUST support, but has no KAUST affiliated authors.",

year = "2020",

month = aug,

doi = "10.1109/led.2020.3006343",

language = "English (US)",

volume = "41",

pages = "1217--1220",

journal = "IEEE Electron Device Letters",

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publisher = "Institute of Electrical and Electronics Engineers",

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AU - Dogan, Tamer

AU - de Riet, Joris

AU - Bel, Thijs

AU - Katsouras, Ilias

AU - Witczak, Lukasz

AU - Kronemeijer, Auke Jisk

AU - Janssen, Rene A. J.

AU - Gelinck, Gerwin H.

N1 - KAUST Repository Item: Exported on 2021-02-11 Acknowledged KAUST grant number(s): OSR-CRG2018-3783 Acknowledgements: This work was supported in part by the European Regional Development Fund through the Flexlines Project through the Interreg V-Program Flanders-The Netherlands, a Cross-Border Cooperation Program, in part by the Province of Noord-Brabant, The Netherlands, and in part by the King Abdullah University of Science and Technology (KAUST) Office for Sponsored Research (OSR) under Award OSR-CRG2018-3783. This publication acknowledges KAUST support, but has no KAUST affiliated authors.

PY - 2020/8

Y1 - 2020/8

N2 - Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.

AB - Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.

UR - http://hdl.handle.net/10754/667318

UR - https://ieeexplore.ieee.org/document/9130793/

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DO - 10.1109/led.2020.3006343

M3 - Article

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EP - 1220

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 8

ER -

1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Abstract

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