β-Ga2O3Pseudo-CMOS Monolithic Inverters

Dhanu Chettri*, Ganesh Mainali, C. Amruth, Vishal Khandelwal, Saravanan Yuvaraja, Na Xiao, Xiao Tang, Derya Baran, Xiaohang Li

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

In this article, we report on the fabrication of β-Ga2O3 pseudo-CMOS inverters using enhancementmode (E-mode) β-Ga2O3 single-finger (SF) and multifinger (MF) thin-film transistors (TFTs). Initially, single-stage monolithic inverter ICs were fabricated using TFTs having threshold voltages VSF th = 0.6 V and VMF th = 0.1 V. However, the single-stage inverter yielded poorer gain (4.50 at VDD, supply voltage = 3 V). Alternatively, a pseudo-CMOS (double-stage) inverter was designed and fabricated, yielding a maximum gain of 6.45 but with a poor noise margin (NM). To improve the NM, the pseudo-CMOS circuit was tested using TFTs having higher threshold voltages (VSF th = 1.85 V and VMF th = 1.75 V). Notably, the optimized pseudo-CMOS circuit exhibited the least peak power consumption (0.2 nW) and the maximum gain of 8 at VDD = 3 V. The monolithically integrated devices performance and IC highlight this technology s remarkable potential for application in the emerging sector of power electronics and extreme-environment electronics.

Original languageEnglish (US)
Pages (from-to)5051-5056
Number of pages6
JournalIEEE TRANSACTIONS ON ELECTRON DEVICES
Volume70
Issue number10
DOIs
StatePublished - Oct 1 2023

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

Keywords

  • inverter logic circuits, pseudo-CMOS
  • β-GaOheteroepitaxy
  • β-GaOthin-film transistors (TFTs)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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